(1) Field of the Invention
The present invention generally relates to etching of resist protective dielectric layer and specifically a protective silicon dioxide layer in the fabrication of a semiconductor device, that may be logic, memory, or a combination thereof.
(2) Description of the Prior Art
During the fabrication of a semiconductor device, parts of the device need to be protected while some other parts are processed. When, for example, memory and logic devices are fabricated on the same chip, electrical contacts on the logic part are made using the salicide (self aligned silicide) process. To enable the selective salicidation of the logic side components, the memory part of the chip is protected by resist protective oxide (RPO) and masked with a resist mask. Another example is the fabrication of a chip with a field effect transistor (FET) device and I/O circuitry provided on the same chip. While forming electrical contacts to the FET elements such as source, drain, and gate with the salicidation process, the I/O part of the chip is protected from several process steps with an RPO film. In all these applications, an RPO film is first deposited and then a resist mask is formed over those areas of the chip that need to be protected from some of the subsequent process steps. The RPO film is then etched in the exposed areas of the chip. RPO etching process is critical, depending upon the application since other oxide films in the unmasked areas of the chip get attacked as well. When wet etching is used, the process will produce undercut profiles near the edge of the resist mask, resulting in poor dimensional control and resist mask peeling and mask lift-off. Resist peeling problems become even more severe as the ground rule dimensions (e.g. line width and spacing) shrink to less than 0.25 μm, with large sections on the wafer floating off during the rinsing step following the etching step.
U.S. Pat. No. 5,863,820 describes a process and structure with both logic and memory devices fabricated on the same chip. Electrical contacts to the memory device are made using a self aligned contact (SAC) process, while the logic device contacts are made with the salicide process. The two processes are integrated within a single chip by first forming poly silicon gate pedestals. Next, oxide or nitride spacers are grown on the vertical side of the gate. Source/drain regions are then formed followed by a coating of RPO film on the memory part of the chip. The RPO film allows selective application of the salicidation process to the logic part only.
U.S. Pat. No. 5,891,771 describes a shallow trench isolated recessed structure that has a low probability of short-circuiting at the silicon to trench interface or between source or drain and the gate. An isolation trench structure having a top portion with vertical sides and a lower portion with sloping sides is first formed. With filled trench along with a poly-silicon gate and gate oxide, the thinner lightly doped N-silicon layer is formed using ion implantation. Spacers are then formed on the gate prior to the second implantation step and a thin layer of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate by the amount of silicon removed. A deeper, more strongly N-type silicon is formed, followed by standard silicidation process using the standard RPO process steps.
U.S. Pat. No. 6,093,593 describes a method of forming a gate that provides reduced recess in adjacent shallow trench isolation (STI). The process begins by forming shallow trench isolation structure on a silicon surface that separates a cell area from an I/O area on a chip. A gate is formed in the cell area adjacent to STI. Impurity ions are implanted into the semiconductor surface adjacent to the gate to form source/drain regions. A resist protective oxide (RPO) layer, having a greater porosity than the oxide filled in STI structure, is then deposited. The RPO is then patterned to form a protective mask over the I/O area, thereby exposing the cell area of the chip. Since RPO has higher etch rate than STI-filled oxide due to higher porosity, very little corner recessing of the STI structure takes place. Silicide contacts are then formed in the usual way. RPO patterning is done with a wet etching process using an aqueous solution of NH4 and HF.
U.S. Pat. No. 6,294,448B1 describes a method to form silicided layers over points of electrical contacts. According to the method, a MOSFET gate electrode is formed, including LDD regions, gate-spacers and source/drain regions. A layer of resist protective oxide (RPO) is deposited over the structure and patterned, leaving the RPO in place where the silicided layers are not to be formed, leaving the surfaces over the source/drain and gate electrode regions exposed. An additional As or B implant is done into the surface of the exposed regions followed by conventional salicidation process. The patent does not describe the RPO etching step except saying it is time-mode dry etching process.
In all the referenced patents, RPO is made use of for selective processing of specific areas of the silicon chip. However, patterning of RPO is not the main objective of these patents. In most cases, RPO patterning is done by a wet etching process with inherent disadvantages listed before. Only in U.S. Pat. No. 6,294,448B1, dry etching is mentioned but as a single step process, with no elucidation of the process. No solutions are proposed in these references on overcoming the disadvantages related to RPO patterning by the single step wet etching or dry etching processes in the prior art.